(1) Field of the Invention
The present invention relates to a computer cluster which has a plurality of nodes, and is to be arranged at each lattice point in an interconnection network having a lattice-like structure.
(2) Description of the Related Art
Recently, the computing performance of the processors has been dramatically improved with the development of the hardware technology. However, currently, some types of processing such as large-scale calculations for science and engineering, massive multimedia data processing, and the like still require computing performance which is much higher than the computing performance of a single processor. In addition, the parallel processing techniques for operating multiple processors in parallel are known. In order to perform parallel processing, an interconnection network in which a plurality of nodes each having a processor and a communication device are mutually linked is constructed. In the interconnection network, data processing proceeds while transmitting packets between the nodes. The interconnection network may be the all-to-all-connection (fully-connected) type, the tree type, the star type, the ring type, the mesh type, the torus type, the hypercube type, or the like.
In the case where the interconnection network contains a great number of nodes, the interconnection network of the mesh type or the torus type is used in many cases in order to suppress increase in the number of links. In the interconnection network of the mesh type or the torus type, the nodes are arranged in a lattice, and packets are relayed through one or more nodes to a destination node. However, in the case where a great number of nodes are interconnected in an interconnection network having a lattice-like structure, the number of nodes arrayed along each direction in the lattice is great, i.e., the number of relay operations which are performed until each packet reaches a destination node is great.
In some techniques proposed for solving the above problem, for example, as disclosed in Japanese Unexamined Patent Publications Nos. 06-35873 and 7-191947, the interconnection network is hierarchized. Specifically, a computer cluster having a plurality of nodes, instead of a single node, is arranged at each lattice point in the interconnection network. In each computer cluster, the plurality of nodes are interconnected so as to form a network of a ring type, a torus type, a hypercube type, or the like. When the interconnection network is hierarchized as above, the average number of operations of relaying a packet can be suppressed, so that the computing performance of the entire system can be improved.
However, according to the techniques disclosed in Japanese Unexamined Patent Publications Nos. 06-35873 and 7-191947, when the operation speed of the processors increases, the packet transfer in each computer cluster causes a bottleneck of the computing performance of the entire system. That is, since each packet is relayed through nodes even in each computer cluster, the relay overhead and the transmission capacity of each link connecting nodes can limit improvement of the computing performance.
On the other hand, if an auxiliary link or switch device is provided in each computer cluster in order to decrease the number of relay operations in each computer cluster, the structure of the computer cluster becomes asymmetric. The relay operation in each node is performed in accordance with an identical rule in an interconnection network having a simple lattice-like structure. However, in the case where the auxiliary link or switch device is provided in each computer cluster, the rule for relaying packets differs depending on nodes, so that the circuitry for realizing the interconnection network becomes complex.